This description relates to device support structures from bulk substrates.
On-chip nanoscale photonic networks are a possible solution for the interconnect bottleneck in high performance CMOS microelectronics, with many additional applications, including telecommunication components, quantum information, and biosensing. Developments in silicon nanophotonics have included silicon-on-insulator (SOI) wafer technology in which a thin silicon device layer is supported by a low-index insulating oxide layer. Optical elements used in planar photonic networks rely on light confinement provided by total internal reflection and/or distributed Bragg reflection, which requires refractive index contrast between the device and surrounding medium.
While high-quality, crystalline, thin film heterolayer structures are readily available for silicon (e.g., as SOI) there remain materials with attractive properties for which high quality thin film heterolayer structures are not available. These include linear and non-linear optical materials including non-linear optical crystals like lithium niobate (LiNbO3) and potassium titanyl phosphate (KTP), silicon-containing materials such as silicon carbide (SiC), III-V semiconductor materials such as III-V nitrides like gallium nitride (GaN) and alloy systems like aluminium gallium nitride (AlGaN), II-IV semiconductor materials such as zinc sulfide (ZnS), metal oxides such as titanium dioxide (TiO2), inert single-crystals such as diamond, and other single-crystal materials. Some of these materials provide advantages for on-chip photonic circuits due to certain beneficial material properties (e.g., compared to silicon). To this end, substantial work has been done to heterogeneously integrate new materials, including those listed above, on foreign substrates. While these efforts have made promising advances, some techniques encounter certain obstacles such as compromised material quality, significant surface roughness, and poor device layer uniformity and reproducibility.